Nehalem .
triple-channel integrated memory controller
three cache levels
hyperthreading
quickpath .
Nehalem codename .
****d on Intel Core microarchitecture. Two to eight cores. Integrated DDR3 triple-channel memory controller. Individual 256 KB L2 memory caches for each core. 8 MB L3 memory cache. New SSE 4.2 instruction set, with the addition of seven new instructions for string and **** processing, collectively called Application Target Accelerators. Two-way simultaneous multi-threading (SMT). Enhancements on the microarchitecture (4-way dispatch unit). Enhancements on the prediction unit, with the addition of a second Branch Target Buffer (BTB). A second 512-entry Translation Look-aside Buffer (TLB). Improved virtualization performance. New QuickPath external bus (two links per CPU socket). 45 nm manufacturing technology.
Nehalem 45
cache
AMD
L2 256
L3 shared 8
L1 Core 2 Duo
Core 2 Duo L2
shared
Core 2 Quad Core 2 Extreme
L2
:
The Socket
With an integrated memory controller, Intel needed a new pinout for Nehalem and the first version with three 64-bit DDR3 memory channels features a 1366-pin LGA interface:
The socket is noticeably bigger than LGA-775 as is the mounting area for heatsinks. You can't reuse LGA-775 heatsinks and instead must use a heatsink with mounting holes more spread apart. As far as we can tell, the same push-pin mounting mechanism from LGA-775 is present in Nehalem which is disappointing.
LGA-1366 (left) vs. LGA-775 (right)
With a larger socket and more pins, the CPU itself is obviously bigger. Here's a shot of our Nehalem compared to a Core 2 Duo E8500:
Nehalem (left) vs. Penryn (right)
Nehalem (left) vs. Penryn (right)
Power Consumption